Elliptic Curve Cryptosystems or, briefly, ECC, appear to be particularly promising for use in smart cards where intrinsic restrictions exist in terms of silicon area and power consumption, while processing time constraints are also to be taken into account.
ECCs make it possible to reach the same level of security of RSA systems using keys of about 200 bits. Operations on elliptic curves are based on the arithmetic of finite Galois fields. Essentially, two basic operations are necessary to implement such a cryptosystem: multiplication and addition in finite fields. While addition is a simple bit-wise X-OR operation, multiplication is inevitably more complex.
For a general review on ECC systems, reference may be made e.g. to M. Rosing, “Implementing Elliptic Curve Cryptography”, Manning Publications, 1999; A. Menezes, “Elliptic Curve Public Key Cryptosystems”, Kluwer Academic Publ., Boston, 6th Printing, 1998; R. Lidl, H. Niederreiter, “Introduction to Finite Fields and their Applications” Cambridge Univ. Press, 1986.
Previous research work concerning practical implementation of ECCs at hardware level are based on co-processor design. A co-processor is essentially a sort of additional arithmetic-logical unit (ALU) adapted to implement the two basic operations of addition and multiplication.
For a general review of previous activity in that area reference can be made e.g. to M. Hasan, “Look-up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems”, in IEEE Trans. on Comp., vol. 49, no. 7, July, 2000; G. Orlando, C. Paar, “A Super-Serial Galois Field Multiplier for FPGA's and its Application to Public-Key Algorithms”, 7th Annual IEEE Symp. on Field-Progr. Custom Computing Machines, 1999, Page(s): 232–239; C. Paar, “Implementation Options for Finite Fields Arithmetic for Elliptic Curve Cryptosystems”, Proc. 3rd Workshop on Elliptic Curve Cryptosystems, ECC '99, Waterloo, Ontario, Canada, November, 1999; L. Song, K. K. Parhi, I. Kuroda, T. Nishitani, “Low-Energy Programmable Finite Field Data Path Architectures”, Proc. ISCAS '98, Vol. 2, 1998, Page(s): 406–409; A. G. Wassal, M. A. Hasan, M. I. Elmasry, “Low-Power Design of Finite Field Multipliers for Wireless Applications”, Proc. 8th Great Lakes Symposium on VLSI, 1998, Page(s): 19–25; H. Wu, M. A. Hasan, “Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields”, in IEEE Trans. on Comp., Vol. 478, August, 1998, Page(s): 883–887; L. Song, K. K. Parhi, “Efficient Finite Field Serial/Parallel Multiplication”, Proc. ASAP '96, 1996, Page(s): 72–82; M. Furer, K. Mehlhorn, “AT2 Optimal Galois Field Multiplier for VLSI”, in IEEE Trans. on Comp., Vol. 389, September 1989, Page(s): 1333–1336.